Fabrication of self-assembled nanowire-type interconnects on a semiconductor device

ABSTRACT

Consistent with an example embodiment, there is a semiconductor device with nanowire-type interconnect elements. 
     The semiconductor device comprises a semiconductor substrate with a pn junction formed by a first doped substrate region of a first conductivity type, and a second doped substrate region of an opposite second conductivity type. There is a layer structure on the semiconductor substrate, the layer structure includes a first metal structure which is conductively connected with the first doped substrate region, and further comprising a second metal structure, which is conductively connected with the second doped substrate region. The layer structure allows the transmission of photons with an energy suitable for creating free charge carriers in the first and second doped substrate regions. A third metal structure comprising at least one self-assembled metal dendrite forms an interconnect element between the first and second metal structures.

The present invention relates to a semiconductor device comprising aself-assembled metal interconnect element and a method for fabricating aself-assembled metal interconnect element on a substrate surface betweena first metal structure and a second metal structure.

The continued reduction of the feature size in microelectronic devicescalls for new methods to fabricate metal interconnect elements.Well-known lithography techniques have become very sophisticated andexpensive since the feature size has moved below the wavelength of lightused for irradiation of resist materials in the lithography process.X-ray and electron-beam lithography are very expensive candidates forproviding high-resolution metal interconnect elements in microelectronicdevices. An alternative method is provided by self-assemblingnanometer-scale interconnect elements, also known as nanowires.

US 2005/0048697 A1 describes self-assembling of nanometer conductivebumps on the basis of carbon nanotubes on a substrate with a metal padon its surface. Such conductive bumps serve to provide a conductiveinterface on chips in a systems-in-package that comprises several chipsconnected by flip-chip technology. However, miniaturization not onlyaffects interface structures to external chips, but also interconnectelements within an interconnect stack of a semiconductor device like amicroelectronic component. However, full integration of carbon nanotubesinto established device processing technologies is still in its infancy.

US 2005/0233158 A1 suggests an electrical interconnect device thatcomprises an organic molecular coating, which is capable of formingelectrically conducting self-assembled monolayers (SAM). A disadvantageof this technique is that such materials are difficult to integrate intohighly developed semiconductor processing.

US 2005/0253220 describes a self-assembly of silicon nanowires andcarbon nanotubes on a microelectronic device. Localized heating isemployed to achieve a thermal requirement for vapor depositionsynthesis. A disadvantage of this method is that it requires thepreparation of a resistive structure for localized heating. Furthermore,the method is restricted to the growth of silicon nanowires and carbonnanotubes, while it is desirable to also be able fabricate metalinterconnect elements.

U.S. Pat. No. 6,323,432 B1 describes a method for fabricating conductivedendrites for a compressible pad-on-pad connector. A particularsubstrate for growth of the dendrites is provided. After growing thedendrites, they are removed from the substrate by etching andsubsequently incorporated into a compressible dielectric material.However, it is a tedious and expensive procedure to grow metal dendriteson one substrate and transfer them onto a target substrate.

The invention has a method aspect and a device aspect. For clarity ofpresentation, the method aspect will be explained first.

Thus, according to a first aspect of the invention, a method forfabricating a self-assembled metal interconnect element on a substratesurface between a first metal structure and a second metal structure isprovided. The method comprises the steps of

-   -   providing a semiconductor substrate with a pn junction formed by        a first doped substrate region of a first conductivity type, and        a second doped substrate region of an opposite second        conductivity type;    -   fabricating a layer structure on the semiconductor substrate,        the layer structure comprising the first metal structure, which        is conductively connected with the first doped substrate region,        and further comprising the second metal structure, which is        conductively connected with the second doped substrate region,        the layer structure allowing transmission of photons with an        energy suitable for creating free charge carriers in the first        and second doped substrate regions;    -   defining an interconnect surface region on the layer structure,        which connects the first and second metal structures and which        is designated for self-assembly of the metal interconnect        element;    -   providing an ambient environment adjacent to the interconnect        surface region and suitable for allowing growth of at least one        metal dendrite between the first and second metal structures;    -   initiating and sustaining self-assembly of a third metal        structure comprising at least one metal dendrite in the        interconnect surface region between the first and second metal        structures until the third metal structure forms the desired        interconnect element, by irradiating the pn junction with        photons of an energy suitable for creating free charge carriers        in the first and second doped substrate regions and thus        creating an electric potential difference between the first and        second metal structures, which is suitable for electrolysis of        metal from at least one of the first and second metal        structures.

The method of the first aspect of the present invention provides asimple and effective way to fabricate a self-assembled interconnectelement between the first and the second metal structures. Theself-assembled metal interconnect element is formed by a third metalstructure that comprises at least one self-assembled metal dendrite. Themethod can easily be integrated into known processing technologies, suchas a CMOS or BiCMOS process.

The method makes use of the fact that irradiation of a pn junctionconnected with the first and second metal structures generates anelectrical potential difference between the first and second metalstructures that is higher the Nernst potential that required forelectrolyzing the metal of the first or second metal structure.

The combination of the semiconductor material used for the pn junctionand of the metal used for the first and second metal structures shouldtherefore be chosen such that the potential generated within thesemiconductor material by illumination with electromagnetic radiation isequal or higher than the Nernst potential of the particular metal. Forexample, illumination of a silicon pn junction with light of an energythat is higher than the bandgap of silicon creates electron-hole pairsand, therefore, a potential difference of about 800 mV between the p-and n regions. For a comparison, the Nernst potential for the process

Cu²⁺+2e⁻→Cu

is 337 mV. Therefore, by providing the connection between the pnjunction and the first and second metal structures, as defined in theabove method definition, a battery potential is provided, which ishigher than the Nernst potential, leading to an electrolysis of Cu.

Therefore, according to a second aspect of the invention, asemiconductor device is provided, comprising:

-   -   a semiconductor substrate with a pn junction formed by a first        doped substrate region of a first conductivity type, and a        second doped substrate region of an opposite second conductivity        type;    -   a layer structure on the semiconductor substrate, the layer        structure comprising the first metal structure, which is        conductively connected with the first doped substrate region,        and further comprising the second metal structure, which is        conductively connected with the second doped substrate region,        the layer structure allowing transmission of photons with an        energy suitable for creating free charge carriers in the first        and second doped substrate regions; and    -   a third metal structure comprising at least one self-assembled        metal dendrite and forming an interconnect element between the        first and second metal structures.

The semiconductor device of the second aspect of the invention forms theproduct achieved by the method of the first aspect of the invention.

Note that the term layer structure is used herein in a broad sense thatcovers various embodiments. The layer structure contains at least onelayer on the semiconductor substrate. By way of example, a layer of aninterconnect stack can form a layer structure according to theinvention. However, a layer structure according to the present inventionmay also contain a stack of two or more single layers.

It is important that the layer structure allows transmission of photonswith an energy suitable for creating free charge carriers in the firstand second doped substrate regions. This can be achieved by letting thelayer structure have transparent lateral sections, which are arranged soas to allow the transmission of light from the surface of the layerstructure to the pn junction. Many dielectric materials, which arecurrently used for the fabrication of an interconnect stack inmicroelectronic devices, are suitable for allowing transmission oflight. Care has to be taken that the layout of the layer structure onthe semiconductor substrate provides a transmission path for theimpinging light in order to create the electrical potential.

A differentiation between a third metal structure and an interconnectelement is made here to distinguish between a fabrication stages, duringwhich a metal structure is formed that initially does not electricallyconnect the first and the second metal structures yet, and a completedinterconnect element, that does provide such electrical connection.Thus, it is after finishing the processing according to the method ofthe first aspect of the invention, the third metal structure forms aninterconnect element between the first and second metal structures.

In the following, preferred embodiments of the method of the firstaspect of the invention and of the semiconductor device of the secondaspect of the invention will be described. The description first turnsto the method of the first aspect of the invention. Here, four differentembodiments, which provide different integration solutions into existingsemiconductor processing technologies will be described in the followingparagraphs.

According to a first embodiment that provides such an integrationsolution, the step of defining the interconnect surface region comprisesfabricating a passivation layer on a surface of the layer structureexcept for the interconnect surface region, the passivation layer beingsuitable for avoiding growth of metal dendrites. The use of apassivation layer allows growing metal dendrites in the unpassivatedsurface regions, which form interconnect surface regions. Suitablematerials that can form the passivation layer are, for instance,corrosion, inhibitors, self-assembled mono layers of suitable substancessuch as a polymer, or other materials known in the art, which canprevent the formation of metal dendrites.

Fabricating the passivation layer on the surface of the layer structureexcept for the interconnect surface region can be accomplished by firstdepositing and laterally structuring a resist layer by well-knowlithographic processes. After lithography, the resist layer only coversthose regions, which shall later on form the interconnect surfaceregions on the layer structure. After that, the passivation layer isfabricated. It may or may not cover the resist sections. Then, theresist-layer sections are stripped from the interconnect surface regionsfor initiating and sustaining the selective formation of metal dendritesin these unpassivated interconnect surface regions.

According to a second integration solution, which forms an alternativeto the previous first integration solution, the step of defining theinterconnect surface region comprises fabricating a resist layer andselectively removing the resist layer only in the desired interconnectsurface region. The present embodiment uses a positive resist processingto form an opening in the resist layer only in the desired interconnectsurface region (or regions). However, a negative resist can also beused. The advantage of this integration solution is that is allows asimplification of the further processing. In one embodiment thestructured resist mask can be used during subsequent application of asurface coating that covers only the interconnect surface region. Thesurface coating is suitable for a stimulating self-assembly of the atleast one metal dendrite. In this embodiment, the resist layer can beremoved after the deposition of the surface coating.

It should be noted that the surface coating can also be applied in thefirst embodiment, using the passivation layer as a mask.

In a further embodiment, which forms a third integration solution, thepositive resist treatment and the surface coating is followed by a stepof removing the resist layer before the step of initiating andsustaining the self-assembly of the third metal structure. In thisembodiment, the dendrite growth is performed selectively only in theregion that is covered with the surface coating, i.e. the interconnectsurface region.

In a further embodiment, which forms a fourth integration solution, thestep of defining the interconnect surface region comprises

-   -   etching a trench in the interconnect surface region    -   fabricating a trench liner on a bottom face of the trench, the        trench liner being suitable for preventing penetration of the        metal of the first and second metal structures.

This embodiment allows fabrication of thicker interconnect elements bydendrite formation, which in a direction pointing away from thesubstrate are flush with the first and second metal structures theyconnect.

Undesired dendrites produced by this method in other substrate regionscan be removed in a subsequent step of chemical mechanical polishing(CMP), which also may be useful in flattening the surface at theposition of the interconnect element formed in the previous processingsteps.

The following embodiments provide different alternatives of ambientenvironments. In a first embodiment, the step of providing an ambientenvironment comprises bringing the interconnect surface region incontact with an aqueous ambient environment to support the electrolysis.

In another embodiment the step of providing an ambient environmentcomprises bringing the interconnect surface region in contact with asolution of a metal. The solution can be an aqueous solution or useanother suitable solvent known in the art of electrolysis. Care shouldbe taken that a solvent is used, which does not attack other materialspresent in the device and exposed to the ambient environment.

In a further embodiment, the step of providing an ambient environmentcomprises bringing the interconnect surface region in contact with anambient environment that has a first humidity level, and a step ofadjusting to a second humidity level. In this embodiment, the humiditylevel can be changed to support the growth of a metal dendrite, andreduced for all other processing steps, as required by the respectiveprocessing steps.

For supporting initial growth of metal dendrites, the step of definingthe interconnect surface region can be preceded by a step ofincorporating metallic contamination into dielectric material extendingbetween the first and second metal structures is performed, and whereina step of removing the metallic contamination is performed afterformation of the interconnect element.

A suitable light source for irradiation of the pn junction is forinstance a laser. However, a lamp may be used as well.

The growth can be accelerated in an embodiment, in which either thefirst or the second or the first and the second metal structures areelectrically charged before or during the step of initiating andsustaining a self-assembly of the third metal structure.

In the following, preferred embodiments of the semiconductor device ofthe second aspect of the invention will be described. It is understoodthat the embodiments can be combined with each other unless statedotherwise explicitly.

In one preferred embodiment, the layer structure forms an interconnectstack comprising a plurality of interconnect levels, and the first orsecond metal structure forms a metal via between adjacent interconnectlevels in the interconnect stack. The present embodiment represents afurther step in miniaturization of interconnect structures, which isachieved by rather uncomplicated processing means, as has been describedabove. The interconnect element that comprises self-assembled metaldendrites forms and interconnect element on a given interconnect level.

In a further embodiment, the pn-junction is formed by doped siliconregions The doped silicon regions are for instance formed by doped wellregions in the substrate.

In a further embodiment of the semiconductor device, at least one of thefirst and second doped substrate regions forms a dummy substrate region,which does not have a function during operation of the semiconductordevice. A function during operation of the semiconductor device isassociated with the application purpose of the particular semiconductordevice. Thus, a dummy substrate region has no influence during theoperation of the electronic device. It can only have the purpose toallow fabrication of the third metal structure.

This way, the respective dummy substrate region is provided to allowformation of the third metal structure along a desired path on the layerstructure even if an electronic circuit, which is formed in thesubstrate, would as such not allow the formation of the third metalstructure along this desired trace. This embodiment thus increases theflexibility in the design of the third metal structure. It also allowsincreasing the length and the flexibility of routing of the third metalstructure on the layer structure.

Furthermore, in one embodiment the semiconductor substrate comprises atleast one dummy pn junction that does not have a function duringoperation of the semiconductor device and at least one pn junction thatdoes have a function during operation of the semiconductor device, andwherein respective first and second metal structures connected withrespective first and second substrate regions of a respective pnjunction are arranged along a trace of the third metal structure on thelayer structure so as to form connections to the substrate regionsaccording to an alternating sequence of the type pnpn etc. or npnp etc.A dummy pn junction that does not have a function during operation ofthe semiconductor device is for instance arranged outside any electroniccircuit that forms a part of the application implemented by thesemiconductor device, or is electrically isolated from such anelectronic circuit.

Note that it is also possible to build the third metal structure only onthe basis of dummy pn junctions.

The third metal structure may be formed of metal dendrites only.Alternatively, it may contain additional metal that is notself-assembled in the form of dendrites.

The third metal structure and at least one of the first and the secondmetal structures preferably comprise copper Cu. Copper is the currentlypreferred metal for interconnect elements because of its low resistanceand low price. Furthermore, the Nernst potential of Cu is low enough toallow performing the processing of the invention with visible light,which is easy to provide.

In the following, further embodiments of the invention will be describedwith reference to the figures.

FIGS. 1-5 show a cross-sectional view of a section of an interconnectstack at different stages during formation of an interconnect elementaccording a first embodiment of the method of the invention.

FIGS. 6-10 show a cross-sectional view of a section of an interconnectstack at different stages during formation of an interconnect elementaccording a second embodiment of the method of the invention.

FIGS. 11-15 show a cross-sectional view of a section of an interconnectstack at different stages during formation of an interconnect elementaccording a third embodiment of the method of the invention.

FIGS. 16-19 show a cross-sectional view of a section of an interconnectstack at different stages during formation of an interconnect elementaccording a fourth embodiment of the method of the invention.

FIG. 20 shows a cross-sectional view of an exemplary semiconductordevice according to an embodiment of the invention.

FIGS. 1-5 show a cross-sectional view of a section of an interconnectstack at different stages during formation of an interconnect elementaccording a first embodiment of the method of the invention.

FIG. 1 shows a cross-sectional view of a layer structure 100 that formsa layer in an interconnect stack, which is arranged on a semiconductorsubstrate (not shown). The layer structure 100 comprises a first metalstructure in the form of a first Cu line 102 and second metal structurein the form of a second Cu line 104. Further Cu lines 106 to 110 areshown. The arrangement of the Cu lines 102 to 110 is completelyexemplary in nature. The Figure only serves to illustrate the presentfirst embodiment of a method for forming an interconnect element betweenthe first Cu line and the second Cu line 104. The arrangement of Culines in real semiconductor devices follows the specific needs of theparticular electronic circuit, which is implemented in the semiconductordevice. A person skilled in the art knows how to translate the technicalteaching given with reference to this exemplary layer structure into areal device.

The Cu lines 102 to 110 are embedded in a dielectric material 112. SinceCu outdiffusion from the lines 102 to 110 can create problems in devicereliability, a liner, an example of which is shown by reference label114, is arranged between each Cu line and the surrounding dielectricmaterial 112. A suitable material for the liner is TiN or TaN. The layerstructure 100 shown in FIG. 1 can be fabricated by well-knowntechniques, such as a dual-damascene technique. In the process offabricating an interconnect stack, the processing stage shown in FIG. 1corresponds to a situation after performing a chemical mechanicalpolishing (CMP) of the surface. At this stage, a surface 116 of thelayer structure 100 is unpassivated.

It is assumed that the first Cu line is conductively connected with afirst doped region in the substrate (not shown). An example ofconnection between the Cu lines and the substrate of will be givenfurther below in FIG. 20. The first doped region has a firstconductivity type such as p-conductivity. The conductive connection withthe p-doped substrate region is provided by underlying interconnectelements and vias, as is well-known for interconnect structures. Thesecond Cu line 104 is assumed to be conductively connected with a seconddoped substrate region, which has the opposite conductivity type incomparison with the first doped region. Therefore, in the presentexample, the Cu line is connected with n-doped region of the substrate.The doped substrate regions can for instance be doped wells or shallowregions such as source and drain regions of field effect transistors(FETs). They form a pn junction.

For the purpose of the present example, it is further assumed that athird metal structure in the form of an interconnect element is to beformed between the first and second Cu lines 102 and 104.

In a first step, the result of which is shown in FIG. 2, a resist layeris deposited on the surface 116 and structured by lithographictechniques to obtain a resist mask 118 that covers the region, in whichthe interconnect element is to be formed. This region is herein referredto as the interconnect surface region. The interconnect surface regiondefined in the processing by specific mask processing may be slightlylarger than the actual interconnect element that is fabricated.

FIG. 3 shows the layer structure of FIG. 2 after a subsequent step ofdepositing a passivation layer 120. The passivation layer covers thesubstrate surface 116 except for the region covered by resist mask 118.Suitable materials for the passivation layer are for instance corrosioninhibitors such as ethylene glycol, polyethylene glycol (PEG),polypropylene glycol (PPG), block co-polymer, polypropylene oxides(PPO), polyethylene oxide (PEO), ammonium dodecyl sulfate, alkyl phenolehter phospate, amino ethyl imadazoline, benzotriazole (BTA), triazole,therophylline, bipyridyl, or other suitable materials in the form of aself-assembled monolayer (SAM).

In a next step, the result of which is shown in FIG. 4, the resist mask118 is stripped, for instance by a selective etching or a dissolvingstep, that leaves the passivation layer 120 and the underlying layerstructure 100 in tact. At this stage, an interconnect surface region 122is defined by an opening in the passivation layer 120, which waspreviously covered by the resist mask 118.

In a next step, self-assembly of metal dendrites is initiated andsustained in a suitable ambient environment, selectively in theinterconnect surface region 122, leading to the formation of a thirdmetal structure 124, cf. FIG. 5. To this end, the pn-junction formed bythe p- and n-type substrate regions is exposed to irradiation, which issymbolized by a “light flash” or “sun” symbol 126.

The light source emits light, which has an energy that is suitable forcreating free charge carriers in the doped substrate region connectedwith the first and second Cu lines 102 and 104. Free charge carriers arecreated by absorption of light of an energy that is above the band gapenergy of the semiconductor material in the doped substrate regions. Thegenerated charge carriers are separated by the built-in potential of thepn-junction and create an electric potential difference between thefirst and second Cu lines 102 and 104. The potential difference is highenough to initiate an sustain electrolysis of Cu from the first orsecond Cu lines 102, 104. In silicon, a potential difference ofapproximately 800 meV is generated by irradiation with light above theband-gap energy of 1.1 eV. Thus, the visible and near infrared spectralrange of electromagnetic radiation up to a wavelength of approximately1000 nm can be used for initiating and sustaining this process.

Of course, the light source could also irradiate the pn-junction with aspectrum that in addition covers energies below the band-gap energy.However, the energy spectrum and spectral intensity distribution of thelight should be chosen so as to generate sufficient numbers of chargecarriers without heating the substrate more than necessary, and inparticular not beyond the tolerable thermal budget.

It should be noted that the dielectric material 112 is selected to betransparent or partly transparent in the suitable spectral range. Inreal device structures, metal structures that may be arranged under thelayer structure 100 should not cover the underlying semiconductorsubstrate to an extent that can block penetration of at least some ofthe irradiated light to the respective pn junctions.

The process is performed in a suitable ambient atmosphere, for instanceby bringing the interconnect surface region in contact with an aqueousambient environment, that in one embodiments contains solved Cu ions.

The electrolyzed Cu created in this process migrates along the surface116 between the two Cu lines and reassembles in the form of at least oneCu dendrite that generally grows in a direction corresponding to that ofthe potential difference. The passivation layer 120 prevents growth ofmetal dendrites in other regions than the interconnect surface region122.

The self-assembly of Cu dendrites is sustained until an interconnectelement with properties suitable for device operation has been formed.The duration of the metal dendrite formation depends the desiredgeometrical parameters of the interconnect element, which can beselected in dependence on the maximum current density expected to betransported by the interconnect element 124. In one embodiment, thelarger the current, the longer is the metal dendrite formation sustainedto obtain a thicker interconnect element with increased stability.

FIGS. 6 to 10 show a cross-sectional view of a section of aninterconnect stack at different stages during formation of aninterconnect element, according a second embodiment of the method of theinvention.

The basic structure shown in FIG. 6 is identical to that of FIG. 1.However, to emphasize the different processing used in this methodembodiment reference labels are used that have the first digit changedfrom “1” to “2” in comparison with the structure of FIG. 1. Unlessstated otherwise explicitly, the structural elements present in themethod embodiment to be described are identical to those that have beendescribed in the context of the previous embodiment of FIGS. 1 to 5. Thefollowing description focuses on the differences in processing. As canbe seen in FIG. 7, the present embodiment uses a positive resistprocessing to define an opening 219 in a resist layer 218 that has beendeposited on the surface 216 of the interconnect layer 200. The opening219 forms an interconnect surface region 222, in which during laterprocessing steps a metal structure will be formed that contains Cudendrites. After formation of the opening 219, a surface coating 220 isdeposited on the surface of the interconnect layer 200. The surfacecoating serves to support the growths of Cu dendrites in laterprocessing steps. A suitable surface coating material is for instance aSilane coupling agent, or a self-assembled monolayer of a suitablematerial. In this step, the resist layer 218 acts as a mask to protectsurface regions other from the interconnect surface region 222 frombeing exposed to the surface coating.

In a next step, the result of which is shown in FIG. 9, the resist layer218 is removed. Note that as an alternative this removal step can beperformed at a later processing stage. If the resist layer 218 is notremoved at the present stage, it will protect the regions where dendritegrowth is unwanted. The resist layer can then be removed after dendritegrowth.

Subsequently, the growth of a third metal structure between the first Culine 202 and the second Cu line 204 is initiated and sustained byirradiation of the pn-junction connected with the Cu lines with light ofa suitable wave length. The third metal structure can have a length ofseveral micrometers between the two Cu lines 202 and 204. Largerdistances are difficult to bridge by dendrite growth without further Custructures. Therefore, for providing the third metal structure over alonger distance, more Cu lines can be provided, which may be connectedto a respective dummy p- or n-type region or, for a pair of Cu lines, toa dummy pn junction. This way, the circuit design can be performedalmost independently from the design of the interconnect stack.

FIGS. 11 to 15 show a cross-sectional view of a section of aninterconnect stack at different stages during formation of aninterconnect element according a third embodiment of the method of theinvention.

The layer structure 300 shown in FIG. 11 is identical to that in FIGS. 6and 1. Again, to emphasize that a different processing is used in thepresent method embodiment, reference labels are used that have a firstdigit “3” but use identical second and third reference labels for likeparts in comparison with FIGS. 1 and 6. Where differences exist in thestructure element despite similar reference labels, these differencesare explicitly described or obvious from a respective figure.

In the present processing embodiment, an interconnect element 324 is tobe formed between the first Cu line 302 and the second Cu line 304. Tothis end, a resist mask 318 is formed by depositing a resist layer andforming an opening 319 in the resist layer, cf. FIG. 12. The processingis similar with that shown in FIG. 7. Note, however, that the opening319 is smaller than the opening 219 and only extends over dielectricmaterial and does not leave any parts of the first and second Cu lines302 and 304 uncovered.

In a subsequent processing step, a trench 321 is formed in thedielectric material 312 at the position of the opening by known etchingtechniques. A bottom wall of the trench 321 is covered with a TiN liner323. It serves at a diffusion barrier for copper, as described beforefor the TiN liner 314 (see description for liner 114 of FIG. 1).

Subsequently, as can be seen in FIG. 14, the resist mask 318 is strippedfrom the surface 316 of the layer structure 300, and growth of a thirdmetal structure comprising Cu dendrites is initiated and sustained byirradiation with light of a suitable energy and intensity. Note againthat as an alternative the removal step can be performed at a laterprocessing stage. If the resist mask 318 is not removed at the presentstage, it will protect the regions where dendrite growth is unwanted.The resist mask 318 can then be removed after dendrite growth.

The growth of the third metal structure 324 is sustained until it isflush with the surface 316. At this stage, unwanted dendrite formationmay occur, which is indicated by reference labels 328 and 330. Suchunwanted dendrites might lead to short circuits. Therefore, a CMP stepis performed subsequently to the dendrite growth to remove all unwantedmetal from the surface 316 and to provide a perfectly flat surface.

FIGS. 16-19 show a cross-sectional view of a section of an interconnectstack at different stages during formation of an interconnect elementaccording a fourth embodiment of the method of the invention.

Again, the layer structure 400 of FIG. 16 is the same as that of FIGS.1, 6, and 11. In the present embodiment, reference labels in the rangeof 400 are used in the same manner as explained for the previousembodiments.

The processing starts with the deposition and lithography of a resistlayer to obtain a resist mask 418 with an opening 419 that defines aninterconnect surface region 422. The opening extends over the distancebetween the first and second Cu lines 402 and 404 and also leaves someof the surface area of these Cu lines open, as in the example of FIG. 7.

In a subsequent step, Cu dendrites are formed in the interconnectsurface region to form a third metal structure 424 resulting in aninterconnect element after stripping of the resist mask 418 (cf. FIGS.18 and 19).

FIG. 20 shows a cross-sectional view of an exemplary semiconductordevice 100 according to an embodiment of the invention.

The semiconductor device 500 comprises a substrate 502, which is made ofp-type silicon. In the substrate, electronic device structures areformed by known methods of semiconductor processing techniques. Thesemiconductor device 500 is a CMOS (ComplementaryMetal-Oxide-Semiconductor) device comprising n-well and p-well regions504 and 506, respectively, in which electronic devices are formed.

The semiconductor device 500 in the cross-sectional view of FIG. 20 isof purely explanatory nature. The device structure shown need not bepresent in a semiconductor device according to the invention. In thepresent example, NMOS and PMOS field effect transistors (FETs) 508 and510 are provided, which are separated by field oxide regions 512, 514,515, and 516.

An interconnect stack 518 is deposited on the substrate and embeds theelectronic devices in dielectric material 520. The electronic devicessuch as the NMOS and PMOS FET 508 and 510, respectively, are contactedby tungsten (W) plugs, such as tungsten plugs 522 and 524, which areconnected with source and drain regions 526 and 528 of PMOS FET 510.

On top of the dielectric layer, typically, a multilevel interconnectstructure is formed using Cu interconnect elements, such as interconnectelements 530 and 532, and Cu lines, such as Cu lines 534 and 536. Culine 534 is connected to the P-well 506, and Cu line 536 is connectedwith N-doped region 526. A pn junction 537 is formed between P-well 506and N-doped region 526.

In the exemplary structure of FIG. 20, only one metal level is shown forreasons of simplicity of presentation. Additional metal levels aretypically present in a semiconductor device. For example, somesemiconductor devices contain up to seven metal levels. The inventioncan be applied on each metal level.

In the semiconductor device 500 of FIG. 20, the lines 534 and 536 form afirst and a second metal structure. An interconnect element 538 isformed between them, which comprises Cu dendrites.

In addition, p+ and n+ regions (not shown) can be integrated so thatthey form a junction, and dendrites will grow between Cu contactingthese regions. The same can be done with n- and p-wells.

While the invention has been illustrated and described in detail in thedrawings and foregoing description, such illustration and descriptionare to be considered illustrative or exemplary and not restrictive; theinvention is not limited to the disclosed embodiments. For instance,growing dendrites between metal vias in an interconnect stack is alsopossible, for example in a process, where only the via level isfabricated, the dendrites are grown, and the line fabrication isperformed subsequently.

Other variations to the disclosed embodiments can be understood andeffected by those skilled in the art in practicing the claimedinvention, from a study of the drawings, the disclosure, and theappended claims. The metal used is not restricted to Cu. Other metalscan be used as well, such as Al, W, or highly-doped (metallicallyconductive) Silicon. Also, the semiconductor material used need not beSilicon. Generally, any semiconductor can be used, also alloys formed ofdifferent semiconductors, such as SiGe, the InAlGaAs alloy system, theInGaAlN alloy system, or others known in the art.

In the claims, the word “comprising” does not exclude other elements orsteps, and the indefinite article “a” or “an” does not exclude aplurality. A single processor or other unit may fulfill the functions ofseveral items recited in the claims. The mere fact that certain measuresare recited in mutually different dependent claims does not indicatethat a combination of these measured cannot be used to advantage.

Any reference signs in the claims should not be construed as limitingthe scope.

1. A semiconductor device, comprising a semiconductor substrate with apn junction formed by a first doped substrate region of a firstconductivity type, and a second doped substrate region of an oppositesecond conductivity type; a layer structure on the semiconductorsubstrate, the layer structure comprising the first metal structure,which is conductively connected with the first doped substrate region,and further comprising the second metal structure, which is conductivelyconnected with the second doped substrate region, the layer structureallowing transmission of photons with an energy suitable for creatingfree charge carriers in the first and second doped substrate regions;and a third metal structure comprising at least one self-assembled metaldendrite and forming an interconnect element between the first andsecond metal structures.
 2. The semiconductor device of claim 1, whereinthe layer structure forms an interconnect stack comprising a pluralityof interconnect levels, and the first or second metal structure forms avia between adjacent interconnect levels in the interconnect stack. 3.The semiconductor device of claim 1, wherein the pn junction is formedby doped silicon regions.
 4. The semiconductor device of claim 1,wherein the third metal structure and at least one of the first and thesecond metal structures comprise Cu.
 5. The semiconductor device ofclaim 1, wherein at least one of the first and second doped substrateregions forms a dummy substrate region, which does not have a functionduring operation of the semiconductor device.
 6. The semiconductordevice of claim 5, wherein the semiconductor substrate comprises atleast one dummy pn junction that does not have a function duringoperation of the semiconductor device and at least one pn junction thatdoes have a function during operation of the semiconductor device, andwherein respective first and second metal structures connected withrespective first and second substrate regions of a respective pnjunction are arranged along a trace of the third metal structure on thelayer structure so as to form connections to the substrate regionsaccording to an alternating sequence of the type pnpn etc. or npnp etc.7-18. (canceled)